2703 search results - page 248 / 541 » Optimizing memory transactions |
183
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CLUSTER
2011
IEEE
14 years 4 months ago
2011
IEEE
—Computing systems will grow significantly larger in the near future to satisfy the needs of computational scientists in areas like climate modeling, biophysics and cosmology. S...
120
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DAC
2009
ACM
16 years 5 months ago
2009
ACM
This paper introduces Way Stealing, a simple architectural modification to a cache-based processor to increase data bandwidth to and from application-specific Instruction Set Exte...
145
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IPPS
2009
IEEE
15 years 11 months ago
2009
IEEE
Partitioned Global Address Space (PGAS) languages provide a unique programming model that can span shared-memory multiprocessor (SMP) architectures, distributed memory machines, o...
123
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GLVLSI
2008
IEEE
15 years 11 months ago
2008
IEEE
Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...
104
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ASAP
2007
IEEE
15 years 10 months ago
2007
IEEE
We present a memory efficient, practical, systolic, parallel architecture for the complete 0/1 knapsack dynamic programming problem, including backtracking. This problem was inte...