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CASES
2001
ACM
15 years 8 months ago
Patchable instruction ROM architecture
Increased systems level integration has meant the movement of many traditionally off chip components onto a single chip including a processor, instruction storage, data path, and ...
Timothy Sherwood, Brad Calder
ISCA
1995
IEEE
118views Hardware» more  ISCA 1995»
15 years 8 months ago
The EM-X Parallel Computer: Architecture and Basic Performance
Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor ...
Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Ha...
ASPLOS
2008
ACM
15 years 6 months ago
Predictor virtualization
Many hardware optimizations rely on collecting information about program behavior at runtime. This information is stored in lookup tables. To be accurate and effective, these opti...
Ioana Burcea, Stephen Somogyi, Andreas Moshovos, B...
ADBIS
2007
Springer
110views Database» more  ADBIS 2007»
15 years 10 months ago
Design of Web Agents Inspired by Brain Research
The paper presents an approach to combine knowledge from memory and brain sciences with information retrieval research in the design of Web agents. An information retrieval agent f...
Maya Dimitrova, Hiroaki Wagatsuma, Yoko Yamaguchi
PLILP
1994
Springer
15 years 8 months ago
Deriving Residual Reference Count Garbage Collectors
We present a strategy to derive an efficient reference count garbage collector for any applicative program by only modifying it on the source code level. The key to the approach is...
Wolfram Schulte