Sciweavers

2703 search results - page 254 / 541
» Optimizing memory transactions
Sort
View
DTJ
1998
171views more  DTJ 1998»
15 years 4 months ago
Measurement and Analysis of C and C++ Performance
ir increasing use of abstraction, modularity, delayed binding, polymorphism, and source reuse, especially when these attributes are used in combination. Modern processor architectu...
Hemant G. Rotithor, Kevin W. Harris, Mark W. Davis
EDBT
2012
ACM
395views Database» more  EDBT 2012»
13 years 6 months ago
Data management with SAPs in-memory computing engine
We present some architectural and technological insights on SAP’s HANA database and derive research challenges for future enterprise application development. The HANA database m...
Joos-Hendrik Boese, Cafer Tosun, Christian Mathis,...
SIGMOD
2004
ACM
128views Database» more  SIGMOD 2004»
16 years 4 months ago
A context-aware methodology for very small data base design
The design of a Data Base to be resident on portable devices and embedded processors for professional systems requires considering both the device memory peculiarities and the mobi...
Cristiana Bolchini, Fabio A. Schreiber, Letizia Ta...
FCCM
2008
IEEE
153views VLSI» more  FCCM 2008»
15 years 11 months ago
A SRAM-based Architecture for Trie-based IP Lookup Using FPGA
Internet Protocol (IP) lookup in routers can be implemented by some form of tree traversal. Pipelining can dramatically improve the search throughput. However, it results in unbal...
Hoang Le, Weirong Jiang, Viktor K. Prasanna
ISCA
2005
IEEE
99views Hardware» more  ISCA 2005»
15 years 10 months ago
Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking
To maintain coherence in conventional shared-memory multiprocessor systems, processors first check other processors’ caches before obtaining data from memory. This coherence che...
Jason F. Cantin, Mikko H. Lipasti, James E. Smith