2703 search results - page 258 / 541 » Optimizing memory transactions |
141
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ICASSP
2011
IEEE
14 years 8 months ago
2011
IEEE
Context based entropy coding has the potential to provide higher gain over memoryless entropy coding. However serious difficulties arise regarding the practical implementation in...
DATE
2006
IEEE
15 years 10 months ago
2006
IEEE
This paper we proposes compiler-based leakage optimization strategy for on-chip scratch-pad memories (SPMs). The idea is to keep only a small set of SPM regions active at a given ...
122
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INFOCOM
2003
IEEE
15 years 9 months ago
2003
IEEE
— Pipelined ASIC architectures are increasingly being used in forwarding engines for high speed IP routers. We explore optimization issues in the design of memory-efficient data...
157
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CODES
2007
IEEE
15 years 10 months ago
2007
IEEE
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
148
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CF
2006
ACM
15 years 8 months ago
2006
ACM
This paper presents our experience mapping OpenMP parallel programming model to the IBM Cyclops-64 (C64) architecture. The C64 employs a many-core-on-a-chip design that integrates...