2703 search results - page 274 / 541 » Optimizing memory transactions |
147
click to vote
ICCS
2005
Springer
15 years 9 months ago
2005
Springer
Cray X1 Fortran and C/C++ compilers provide a number of loop transformations, notably vectorization and multistreaming, in order to exploit the multistreaming processor (MSP) hard...
115
click to vote
ISCA
2002
IEEE
15 years 9 months ago
2002
IEEE
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations...
154
click to vote
ISSS
2002
IEEE
15 years 9 months ago
2002
IEEE
Software pipelining and unfolding are commonly used techniques to increase parallelism for DSP applications. However, these techniques expand the code size of the application sign...
121
click to vote
SIGGRAPH
1999
ACM
15 years 8 months ago
1999
ACM
Bus traffic between the graphics subsystem and memory can become a bottleneck when rendering geometrically complex meshes. In this paper, we investigate the use of vertex caching...
130
click to vote
EUROPAR
1998
Springer
15 years 8 months ago
1998
Springer
This paper aims to improve locality of references by suitably choosing array layouts. We use a new definition of spatial reuse vectors that takes into account memory layout of arra...