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CC
2003
Springer
192views System Software» more  CC 2003»
15 years 9 months ago
Address Register Assignment for Reducing Code Size
Abstract. In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance since studies of programs have shown that in...
Mahmut T. Kandemir, Mary Jane Irwin, Guilin Chen, ...
FPL
2009
Springer
101views Hardware» more  FPL 2009»
15 years 8 months ago
An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure
The creation and optimization of FPGA accelerators comprising several compute cores and memories are challenging tasks in high performance reconfigurable computing. In this paper...
Tobias Schumacher, Christian Plessl, Marco Platzne...
EUROGP
2000
Springer
177views Optimization» more  EUROGP 2000»
15 years 7 months ago
Register Based Genetic Programming on FPGA Computing Platforms
The use of FPGA based custom computing platforms is proposed for implementing linearly structured Genetic Programs. Such a context enables consideration of micro architectural and ...
Malcolm I. Heywood, A. Nur Zincir-Heywood
IWMM
2010
Springer
173views Hardware» more  IWMM 2010»
15 years 9 months ago
CETS: compiler enforced temporal safety for C
Temporal memory safety errors, such as dangling pointer dereferences and double frees, are a prevalent source of software bugs in unmanaged languages such as C. Existing schemes t...
Santosh Nagarakatte, Jianzhou Zhao, Milo M. K. Mar...
168
Voted
ACMMSP
2004
ACM
131views Hardware» more  ACMMSP 2004»
15 years 9 months ago
Reuse-distance-based miss-rate prediction on a per instruction basis
Feedback-directed optimization has become an increasingly important tool in designing and building optimizing compilers. Recently, reuse-distance analysis has shown much promise i...
Changpeng Fang, Steve Carr, Soner Önder, Zhen...