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MICRO
2006
IEEE
155views Hardware» more  MICRO 2006»
15 years 10 months ago
In-Network Cache Coherence
With the trend towards increasing number of processor cores in future chip architectures, scalable directory-based protocols for maintaining cache coherence will be needed. Howeve...
Noel Eisley, Li-Shiuan Peh, Li Shang
ICS
2005
Tsinghua U.
15 years 9 months ago
Improving the computational intensity of unstructured mesh applications
Although unstructured mesh algorithms are a popular means of solving problems across a broad range of disciplines—from texture mapping to computational fluid dynamics—they ar...
Brian S. White, Sally A. McKee, Bronis R. de Supin...
IEEEINTERACT
2003
IEEE
15 years 9 months ago
High Performance Code Generation through Lazy Activation Records
For call intensive programs, function calls are major bottlenecks during program execution since they usually force register contents to be spilled into memory. Such register to m...
Manoranjan Satpathy, Rabi N. Mahapatra, Siddharth ...
156
Voted
CASES
2003
ACM
15 years 9 months ago
Frequent loop detection using efficient non-intrusive on-chip hardware
Dynamic software optimization methods are becoming increasingly popular for improving software performance and power. The first step in dynamic optimization consists of detecting ...
Ann Gordon-Ross, Frank Vahid
138
Voted
ICPP
1991
IEEE
15 years 7 months ago
Emulation of a PRAM on Leveled Networks
There is an interesting class of ICNs, which includes the star graph and the n-way shuffle, for which the network diameter is sub-logarithmic in the network size. This paper prese...
Michael A. Palis, Sanguthevar Rajasekaran, David S...