2703 search results - page 303 / 541 » Optimizing memory transactions |
134
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ISCA
2005
IEEE
15 years 9 months ago
2005
IEEE
The load-store unit is a performance critical component of a dynamically-scheduled processor. It is also a complex and non-scalable component. Several recently proposed techniques...
136
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ICCAD
2001
IEEE
16 years 29 days ago
2001
IEEE
Abstract: We propose an effective algorithm for power optimization in behavioral synthesis. In previous work, it has been shown that several hardware allocation/binding problems fo...
168
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LCTRTS
2005
Springer
15 years 9 months ago
2005
Springer
Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly preval...
140
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ISCA
1999
IEEE
15 years 8 months ago
1999
IEEE
State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-oforder engine, the instruction scheduler is responsible for disp...
130
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AUTOMATICA
2006
15 years 4 months ago
2006
This paper is concerned with the optimal control of linear discrete-time systems, which are subject to unknown but bounded state disturbances and mixed constraints on the state an...