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129
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DATE
2003
IEEE
97views Hardware» more  DATE 2003»
15 years 9 months ago
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...
G. Surendra, Subhasis Banerjee, S. K. Nandy
122
Voted
ICPP
2003
IEEE
15 years 9 months ago
Scheduling Algorithms with Bus Bandwidth Considerations for SMPs
The bus that connects processors to memory is known to be a major architectural bottleneck in SMPs. However, both software and scheduling policies for these systems generally focu...
Christos D. Antonopoulos, Dimitrios S. Nikolopoulo...
126
Voted
PPOPP
2003
ACM
15 years 8 months ago
Compactly representing parallel program executions
Collecting a program’s execution profile is important for many reasons: code optimization, memory layout, program debugging and program comprehension. Path based execution pro...
Ankit Goel, Abhik Roychoudhury, Tulika Mitra
131
Voted
VLSID
2000
IEEE
94views VLSI» more  VLSID 2000»
15 years 8 months ago
A Genetic Algorithm for the Synthesis of Structured Data Paths
The technique presented here achieves simultaneous optimization of schedule time and data path component cost within a structured data path architecture, using a genetic algorithm...
Chittaranjan A. Mandal, R. M. Zimmer
118
Voted
GIS
1999
ACM
15 years 8 months ago
A Provably Efficient Computational Model for Approximate Spatiotemporal Retrieval
: The paper is concerned with the effective and efficient processing of spatiotemporal selection queries under varying degrees of approximation. Such queries may employ operators l...
Vasilis Delis, Christos Makris, Spyros Sioutas