2703 search results - page 416 / 541 » Optimizing memory transactions |
147
Voted
TWC
2010
14 years 10 months ago
2010
Relay selection for cooperative communications promises significant performance improvements, and is, therefore, attracting, considerable attention. While several criteria have be...
170
Voted
ISPD
2012
ACM
13 years 11 months ago
2012
ACM
In this paper, we propose a new approach for gated bus synthesis [16] with minimum wire capacitance per transaction in three-dimensional (3D) ICs. The 3D IC technology connects di...
166
Voted
IWOMP
2007
Springer
15 years 9 months ago
2007
Springer
The Cell processor is a heterogeneous multi-core processor with one Power Processing Engine (PPE) core and eight Synergistic Processing Engine (SPE) cores. Each SPE has a directly...
130
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ICPP
1998
IEEE
15 years 7 months ago
1998
IEEE
Many large scale applications, have significant I/O requirements as well as computational and memory requirements. Unfortunately, limited number of I/O nodes provided by the conte...
154
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ISCAPDCS
2007
15 years 4 months ago
2007
— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...