Sciweavers

2703 search results - page 448 / 541
» Optimizing memory transactions
Sort
View
117
Voted
IPPS
2008
IEEE
15 years 7 months ago
High performance MPEG-2 software decoder on the cell broadband engine
The Sony-Toshiba-IBM Cell Broadband Engine is a heterogeneous multicore architecture that consists of a traditional microprocessor (PPE) with eight SIMD coprocessing units (SPEs) ...
David A. Bader, Sulabh Patel
GECCO
2007
Springer
181views Optimization» more  GECCO 2007»
15 years 7 months ago
ACOhg: dealing with huge graphs
Ant Colony Optimization (ACO) has been successfully applied to those combinatorial optimization problems which can be translated into a graph exploration. Artificial ants build s...
Enrique Alba, J. Francisco Chicano
IEEEPACT
2005
IEEE
15 years 6 months ago
HUNTing the Overlap
Hiding communication latency is an important optimization for parallel programs. Programmers or compilers achieve this by using non-blocking communication primitives and overlappi...
Costin Iancu, Parry Husbands, Paul Hargrove
MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
15 years 6 months ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
CASES
2007
ACM
15 years 4 months ago
A low power front-end for embedded processors using a block-aware instruction set
Energy, power, and area efficiency are critical design concerns for embedded processors. Much of the energy of a typical embedded processor is consumed in the front-end since inst...
Ahmad Zmily, Christos Kozyrakis