2703 search results - page 459 / 541 » Optimizing memory transactions |
97
Voted
MICRO
2009
IEEE
15 years 7 months ago
2009
IEEE
Aggressive prefetching is very beneficial for memory latency tolerance of many applications. However, it faces significant challenges in multi-core systems. Prefetchers of diff...
106
Voted
MICRO
2009
IEEE
15 years 7 months ago
2009
IEEE
A platform that supported Sequential Consistency (SC) for all codes — not only the well-synchronized ones — would simplify the task of programmers. Recently, several hardware ...
108
click to vote
CIVR
2009
Springer
15 years 7 months ago
2009
Springer
The GIST descriptor has recently received increasing attention in the context of scene recognition. In this paper we evaluate the search accuracy and complexity of the global GIST...
106
Voted
EUROPAR
2009
Springer
15 years 7 months ago
2009
Springer
An upgrade from dual-core to quad-core AMD processor on the Cray XT system at the Oak Ridge National Laboratory (ORNL) Leadership Computing Facility (LCF) has resulted in significa...
120
Voted
ICCS
2009
Springer
15 years 7 months ago
2009
Springer
Irregular and sparse scientific computing programs frequently experience performance losses due to inefficient use of the memory system in most machines. Previous work has shown t...