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98
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DATE
2003
IEEE
127views Hardware» more  DATE 2003»
15 years 6 months ago
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
Amit Agarwal, Kaushik Roy, T. N. Vijaykumar
98
Voted
ICDAR
2003
IEEE
15 years 6 months ago
A Low-Cost Parallel K-Means VQ Algorithm Using Cluster Computing
In this paper we propose a parallel approach for the Kmeans Vector Quantization (VQ) algorithm used in a twostage Hidden Markov Model (HMM)-based system for recognizing handwritte...
Alceu de Souza Britto Jr., Paulo Sergio Lopes de S...
163
Voted
ICTAI
2003
IEEE
15 years 6 months ago
Approximate Discrete Probability Distribution Representation Using a Multi-Resolution Binary Tree
Computing and storing probabilities is a hard problem as soon as one has to deal with complex distributions over multiples random variables. The problem of efficient representati...
David Bellot, Pierre Bessière
116
Voted
IEEEPACT
2003
IEEE
15 years 6 months ago
Compilation, Architectural Support, and Evaluation of SIMD Graphics Pipeline Programs on a General-Purpose CPU
Graphics and media processing is quickly emerging to become one of the key computing workloads. Programmable graphics processors give designers extra flexibility by running a sma...
Mauricio Breternitz Jr., Herbert H. J. Hum, Sanjee...
112
Voted
LCN
2003
IEEE
15 years 6 months ago
Evaluating System Performance in Gigabit Networks
- With the current wide deployment of Gigabit Ethernet technology in the backbone and workgroup switches, the network performance bottleneck has shifted for the first time in nearl...
Khaled Salah, K. El-Badawi