2703 search results - page 477 / 541 » Optimizing memory transactions |
119
Voted
MICRO
1999
IEEE
15 years 5 months ago
1999
IEEE
Compressing the instructions of an embedded program is important for cost-sensitive low-power control-oriented embedded computing. A number of compression schemes have been propos...
113
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ICS
1999
Tsinghua U.
15 years 5 months ago
1999
Tsinghua U.
Hydra is a chip multiprocessor (CMP) with integrated support for thread-level speculation. Thread-level speculation provides a way to parallelize sequential programs without the n...
128
Voted
HPCA
1998
IEEE
15 years 5 months ago
1998
IEEE
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
90
Voted
IPPS
1998
IEEE
15 years 5 months ago
1998
IEEE
Software DSMs have been a research topic for over a decade. While good performance has been achieved in some cases, consistent performance has continued to elude researchers. This...
93
Voted
IPPS
1998
IEEE
15 years 5 months ago
1998
IEEE
LAPI is a low-level, high-performance communication interface available on the IBM RS/6000 SP system. It provides an activemessage-like interface along with remote memory copy and...