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» Optimizing pipelines for power and performance
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ISVLSI
2003
IEEE
157views VLSI» more  ISVLSI 2003»
15 years 7 months ago
Joint Minimization of Power and Area in Scan Testing by Scan Cell Reordering
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...
Shalini Ghosh, Sugato Basu, Nur A. Touba
142
Voted
ACMSE
2004
ACM
15 years 7 months ago
Execution characteristics of SPEC CPU2000 benchmarks: Intel C++ vs. Microsoft VC++
Modern processors include features such as deep pipelining, multilevel cache hierarchy, branch predictors, out of order execution engine, and advanced floating point and multimedi...
Swathi Tanjore Gurumani, Aleksandar Milenkovic
AAIM
2005
Springer
119views Algorithms» more  AAIM 2005»
15 years 3 months ago
Locating Performance Monitoring Mobile Agents in Scalable Active Networks
The idea of active networks has been emerged in recent years to increase the processing power inside the network. The intermediate nodes such as routers will be able to host mobile...
Amir Hossein Hadad, Mehdi Dehghan, Hossein Pedram
124
Voted
FCCM
2006
IEEE
144views VLSI» more  FCCM 2006»
15 years 7 months ago
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
Robert G. Dimond, Oskar Mencer, Wayne Luk
JCM
2008
196views more  JCM 2008»
15 years 1 months ago
An Energy Optimization Protocol Based on Cross-Layer for Wireless Sensor Networks
Survivability is one of the critical issues and the most important research topics in the fields of wireless sensor networks (WSNs). Energy efficiency is one of the determining fac...
Yuebin Bai, Shujuan Liu, Mo Sha, Yang Lu, Cong Xu