2048 search results - page 115 / 410 » Optimizing pipelines for power and performance |
FPL
2003
Springer
15 years 7 months ago
2003
Springer
The power-efficient implementation of motion estimation algorithms on a system comprised by an FPGA and an external memory is presented. Low power consumption is achieved by implem...
110
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TCOM
2008
15 years 1 months ago
2008
This paper applies the concept of balanced capacity (a tradeoff between performance and fairness) to the uplink of a frequency-selective multiuser channel. Individual power constr...
143
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DAC
1997
ACM
15 years 6 months ago
1997
ACM
This paper describes a new design methodology to analyze the on-chip power supply noise for high performance microprocessors. Based on an integrated package-level and chip-level p...
ICASSP
2009
IEEE
15 years 8 months ago
2009
IEEE
— In this paper we consider the optimization of transceivers which use the nonlinear vector perturbation technique at the transmitter. Since the perturbation vector can be almost...
130
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CODES
2007
IEEE
15 years 8 months ago
2007
IEEE
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...