2048 search results - page 124 / 410 » Optimizing pipelines for power and performance |
110
Voted
CHES
2005
Springer
15 years 7 months ago
2005
Springer
Two new FPGA designs for the Advanced Encryption Standard (AES) are presented. The first is believed to be the fastest, achieving 25 Gbps throughput using a Xilinx Spartan-III (XC3...
123
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IAJIT
2010
15 years 9 days ago
2010
: This paper proposes a pipelined, systolic architecture for two- dimensional discrete Fourier transform computation which is highly concurrent. The architecture consists of two, o...
ICMCS
2006
IEEE
15 years 7 months ago
2006
IEEE
This paper proposes a new architecture for efficient variable-length decoding (VLD) of entropy-coded data for multimedia applications on general-purpose processors. It improves o...
218
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DAC
2011
ACM
14 years 1 months ago
2011
ACM
The deployment of computer vision algorithms in mobile applications is growing at a rapid pace. A primary component of the computer vision software pipeline is feature extraction,...
108
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ISPASS
2010
IEEE
15 years 8 months ago
2010
IEEE
After many years of prefetching research, most commercially available systems support only two types of prefetching: software-directed prefetching and hardware-based prefetchers u...