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» Optimizing pipelines for power and performance
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VLSID
2001
IEEE
169views VLSI» more  VLSID 2001»
16 years 2 months ago
Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits
Development of the process technology for dual threshold (dual Vth ) CMOS circuit has opened up the possibility of using it to reduce static power in low voltage high performance ...
Nikhil Tripathi, Amit M. Bhosle, Debasis Samanta, ...
VTC
2007
IEEE
15 years 8 months ago
Power Allocation Scheme for MIMO MC-CDMA With Two Dimensional Spreading
— In this paper, we develop a power distribution scheme for multi-input multi-output (MIMO) [1] multi-carrier (MC) code division multiple access (CDMA) systems [2]-[3] with two-d...
Wladimir Bocquet, Kazunori Hayashi, Hideaki Sakai
ISLPED
2003
ACM
85views Hardware» more  ISLPED 2003»
15 years 7 months ago
Low power coordination in wireless ad-hoc networks
Distributed wireless ad-hoc networks (DWANs) pose numerous technical challenges. Among them, two are widely considered as crucial: autonomous localized operation and minimization ...
Farinaz Koushanfar, Abhijit Davare, Dai Tho Nguyen...
111
Voted
EUROPAR
2010
Springer
15 years 1 months ago
Power-Efficient Spilling Techniques for Chip Multiprocessors
Abstract. Current trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the ...
Enric Herrero, José González, Ramon ...
137
Voted
ICC
2008
IEEE
171views Communications» more  ICC 2008»
15 years 8 months ago
On the Capacity of Training-Based Transmissions with Input Peak Power Constraints
— 1 In this paper, training-based transmissions over a priori unknown Rayleigh block fading channels are considered. The input signals are assumed to be subject to peak power con...
Mustafa Cenk Gursoy