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» Optimizing pipelines for power and performance
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DATE
2007
IEEE
100views Hardware» more  DATE 2007»
14 years 9 months ago
A new pipelined implementation for minimum norm sorting used in square root algorithm for MIMO-VBLAST systems
Multiple Input - Multiple Output (MIMO) wireless technology involves highly complex vectors and matrix computations which are directly related to increased power and area consumpt...
Zahid Khan, Tughrul Arslan, John S. Thompson, Ahme...
VLSID
2007
IEEE
210views VLSI» more  VLSID 2007»
15 years 10 months ago
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
Phillip H. Jones, Young H. Cho, John W. Lockwood
62
Voted
DAC
2007
ACM
15 years 10 months ago
Self-Resetting Latches for Asynchronous Micro-Pipelines
Asynchronous circuits are increasingly attractive as low power or high-performance replacements to synchronous designs. A key part of these circuits are asynchronous micropipeline...
Tiberiu Chelcea, Girish Venkataramani, Seth Copen ...
VLSID
2004
IEEE
138views VLSI» more  VLSID 2004»
15 years 10 months ago
Synthesis-driven Exploration of Pipelined Embedded Processors
Recent advances on language based software toolkit generation enables performance driven exploration of embedded systems by exploiting the application behavior. There is a need fo...
Prabhat Mishra, Arun Kejariwal, Nikil Dutt
SBCCI
2003
ACM
94views VLSI» more  SBCCI 2003»
15 years 2 months ago
A New Pipelined Array Architecture for Signed Multiplication
– We present a new architecture for signed multiplication which maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. This...
Eduardo A. C. da Costa, Sergio Bampi, José ...