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» Optimizing pipelines for power and performance
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DATE
2007
IEEE
85views Hardware» more  DATE 2007»
15 years 8 months ago
Low-power warp processor for power efficient high-performance embedded systems
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
Roman L. Lysecky
ISPD
1999
ACM
97views Hardware» more  ISPD 1999»
15 years 6 months ago
A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design
This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTL-design and early flo...
Masato Iwabuchi, Noboru Sakamoto, Yasushi Sekine, ...
ICASSP
2010
IEEE
15 years 2 months ago
Joint bandwidth and power allocation in wireless multi-user decode-and-forward relay networks
The resource allocation problem in wireless multi-user decode-and-forward (DF) relay networks is considered. The conventional resource allocation schemes based on the equal distri...
Xiaowen Gong, Sergiy A. Vorobyov, Chintha Tellambu...
ESTIMEDIA
2005
Springer
15 years 7 months ago
Custom Processor Design Using NISC: A Case-Study on DCT algorithm
Designing Application-Specific Instruction-set Processors (ASIPs) usually requires designing a custom datapath, and modifying instruction-set, instruction decoder, and compiler. A...
Bita Gorjiara, Daniel D. Gajski
CVPR
2009
IEEE
15 years 5 months ago
Towards high-resolution large-scale multi-view stereo
Boosted by the Middlebury challenge, the precision of dense multi-view stereovision methods has increased drastically in the past few years. Yet, most methods, although they perfo...
Vu Hoang Hiep, Renaud Keriven, Patrick Labatut, Je...