2048 search results - page 13 / 410 » Optimizing pipelines for power and performance |
SIGGRAPH
1994
ACM
15 years 1 months ago
1994
ACM
This paper describes the design and implementation of IRIS Performer, a toolkit for visual simulation, virtual reality, and other real-time 3D graphics applications. The principal...
ASPDAC
1999
ACM
15 years 1 months ago
1999
ACM
We describe a high performance clocking methodology for domino pipelines. Our technique maximizes the clock rate of the circular pipeline (“ring”) while maintaining the ring c...
MICRO
2009
IEEE
15 years 4 months ago
2009
IEEE
Performance and power are the first order design metrics for Network-on-Chips (NoCs) that have become the de-facto standard in providing scalable communication backbones for mult...
71
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HPCA
2008
IEEE
15 years 10 months ago
2008
IEEE
Power control is becoming a key challenge for effectively operating a modern data center. In addition to reducing operating costs, precisely controlling power consumption is an es...
100
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RSP
2003
IEEE
15 years 2 months ago
2003
IEEE
As embedded systems continue to face increasingly higher performance requirements, deeply pipelined processor architectures are being employed to meet desired system performance. ...