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» Optimizing pipelines for power and performance
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IESS
2007
Springer
156views Hardware» more  IESS 2007»
15 years 8 months ago
Automatic Data Path Generation from C code for Custom Processors
The stringent performance constraints and short time to market of modern digital systems require automatic methods for design of high performance applicationspecific architectures...
Jelena Trajkovic, Daniel Gajski
DAC
2005
ACM
16 years 2 months ago
Hardware speech recognition for user interfaces in low cost, low power devices
We propose a system architecture for real-time hardware speech recognition on low-cost, power-constrained devices. The system is intended to support real-time speech-based user in...
Sergiu Nedevschi, Rabin K. Patra, Eric A. Brewer
DATE
2005
IEEE
111views Hardware» more  DATE 2005»
15 years 3 months ago
Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures
In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consump...
Suresh Srinivasan, Lin Li, Narayanan Vijaykrishnan
CVBIA
2005
Springer
15 years 7 months ago
Segmenting Brain Tumors with Conditional Random Fields and Support Vector Machines
Abstract. Markov Random Fields (MRFs) are a popular and wellmotivated model for many medical image processing tasks such as segmentation. Discriminative Random Fields (DRFs), a dis...
Chi-Hoon Lee, Mark Schmidt, Albert Murtha, Aalo Bi...
ISCA
2011
IEEE
271views Hardware» more  ISCA 2011»
14 years 5 months ago
CRIB: consolidated rename, issue, and bypass
Conventional high-performance processors utilize register renaming and complex broadcast-based scheduling logic to steer instructions into a small number of heavily-pipelined exec...
Erika Gunadi, Mikko H. Lipasti