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» Optimizing pipelines for power and performance
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TVLSI
2008
74views more  TVLSI 2008»
15 years 1 months ago
Stack Sizing for Optimal Current Drivability in Subthreshold Circuits
Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors in...
John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S....
93
Voted
ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
15 years 7 months ago
Data marshaling for multi-core architectures
Previous research has shown that Staged Execution (SE), i.e., dividing a program into segments and executing each segment at the core that has the data and/or functionality to bes...
M. Aater Suleman, Onur Mutlu, José A. Joao,...
ICCAD
1991
IEEE
100views Hardware» more  ICCAD 1991»
15 years 5 months ago
Layout Driven Logic Restructuring/Decomposition
As feature sizes decrease and chip sizes increase, the area and performance of chips become dominated by the interconnect. In spite of this trend, most existing synthesis systems ...
Massoud Pedram, Narasimha B. Bhat
118
Voted
CODES
2008
IEEE
15 years 2 months ago
Methodology for multi-granularity embedded processor power model generation for an ESL design flow
With power becoming a major constraint for multi-processor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is cr...
Young-Hwan Park, Sudeep Pasricha, Fadi J. Kurdahi,...
INFOCOM
2008
IEEE
15 years 8 months ago
Power Awareness in Network Design and Routing
Abstract—Exponential bandwidth scaling has been a fundamental driver of the growth and popularity of the Internet. However, increases in bandwidth have been accompanied by increa...
Joseph Chabarek, Joel Sommers, Paul Barford, Crist...