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» Optimizing pipelines for power and performance
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VLSID
2002
IEEE
122views VLSI» more  VLSID 2002»
16 years 2 months ago
Evaluating Run-Time Techniques for Leakage Power Reduction
While some leakage power reduction techniques require modification of process technology achieving savings at the fabrication stage, others are based on circuit-level optimization...
David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishn...
121
Voted
ICC
2009
IEEE
144views Communications» more  ICC 2009»
15 years 8 months ago
Power Allocation for Multi-Access Two-Way Relaying
—We consider a multi-access two-way relay network where multiple pairs of users exchange information with their pre-assigned partners with the assistance of an intermediate relay...
Min Chen, Aylin Yener
DATE
2008
IEEE
117views Hardware» more  DATE 2008»
15 years 8 months ago
A Scalable Algorithmic Framework for Row-Based Power-Gating
Leakage power is a serious concern in nanometer CMOS technologies. In this paper we focus on leakage reduction through automatic insertion of sleep transistors for power gating in...
Ashoka Visweswara Sathanur, Antonio Pullini, Luca ...
110
Voted
VTC
2008
IEEE
123views Communications» more  VTC 2008»
15 years 8 months ago
A Low-Complexity Iterative Power Allocation Scheme for Multiuser OFDM Systems
—Multiuser orthogonal frequency division multiplexing (MU-OFDM) is a promising technique for future wide-area mobile communications, which can provide scalable high data rate tra...
Chin-Liang Wang, Chiuan-Hsu Chen
107
Voted
ICCD
2007
IEEE
99views Hardware» more  ICCD 2007»
15 years 5 months ago
Power reduction of chip multi-processors using shared resource control cooperating with DVFS
This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can ...
Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Tak...