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» Optimizing pipelines for power and performance
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INFOCOM
2009
IEEE
15 years 8 months ago
Power Controlled Scheduling with Consecutive Transmission Constraints: Complexity Analysis and Algorithm Design
Abstract—We study the joint power control and minimumframe-length scheduling problem in wireless networks, under the physical interference model and subject to consecutive transm...
Liqun Fu, Soung Chang Liew, Jianwei Huang
127
Voted
ICC
2008
IEEE
127views Communications» more  ICC 2008»
15 years 8 months ago
Power and Bandwidth Allocation in Cooperative Dirty Paper Coding
—The cooperative dirty paper coding (DPC) rate region is investigated in a two-transmitter two-receiver network with full channel state information available at all terminals. Th...
Chris T. K. Ng, Nihar Jindal, Andrea J. Goldsmith,...
ASPDAC
2007
ACM
119views Hardware» more  ASPDAC 2007»
15 years 5 months ago
Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space
Parallel prefix adder is the most flexible and widely-used binary adder for ASIC designs. Many high-level synthesis techniques have been developed to find optimal prefix structures...
Jianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng,...
WIOPT
2010
IEEE
15 years 6 days ago
Low complexity algorithms for relay selection and power control in interference-limited environments
Abstract—We consider an interference-limited wireless network, where multiple source-destination pairs compete for the same pool of relay nodes. In an attempt to maximize the sum...
Lazaros Gkatzikis, Iordanis Koutsopoulos
DAC
2003
ACM
16 years 2 months ago
Distributed sleep transistor network for power reduction
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the ...
Changbo Long, Lei He