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» Optimizing pipelines for power and performance
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ISLPED
2006
ACM
117views Hardware» more  ISLPED 2006»
15 years 3 months ago
Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm)
As transistors continue to scale down into the nanometer regime, device leakage currents are becoming the dominant cause of power dissipation in nanometer caches, making it essent...
Samuel Rodríguez, Bruce L. Jacob
PATMOS
2004
Springer
15 years 3 months ago
SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level
We present SoftExplorer, a tool to estimate and analyze the power and energy consumption of an algorithm from the C program. The consumption of every loop is analyzed, and the inï¬...
Eric Senn, Johann Laurent, Nathalie Julien, Eric M...
AMW
2010
14 years 11 months ago
Run-time Optimization for Pipelined Systems
Traditional optimizers fail to pick good execution plans, when faced with increasingly complex queries and large data sets. This failure is even more acute in the context of XQuery...
Riham Abdel Kader, Maurice van Keulen, Peter A. Bo...
ISCA
2002
IEEE
108views Hardware» more  ISCA 2002»
15 years 2 months ago
The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays
Microprocessor clock frequency has improved by nearly 40% annually over the past decade. This improvement has been provided, in equal measure, by smaller technologies and deeper p...
M. S. Hrishikesh, Doug Burger, Stephen W. Keckler,...
BMCBI
2007
166views more  BMCBI 2007»
14 years 9 months ago
Data handling strategies for high throughput pyrosequencers
Background: New high throughput pyrosequencers such as the 454 Life Sciences GS 20 are capable of massively parallelizing DNA sequencing providing an unprecedented rate of output ...
Gabriele A. Trombetti, Raoul J. P. Bonnal, Ermanno...