Sciweavers

2048 search results - page 17 / 410
» Optimizing pipelines for power and performance
Sort
View
CONPAR
1994
15 years 1 months ago
A Framework for Resource-Constrained Rate-Optimal Software Pipelining
The rapid advances in high-performancecomputer architectureand compilationtechniques provide both challenges and opportunitiesto exploitthe rich solution space of software pipeline...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...
MEMOCODE
2010
IEEE
14 years 7 months ago
Elastic systems
Elastic systems provide tolerance to the variations in computation and communication delays. The incorporation of elasticity opens new opportunities for optimization using new corr...
Jordi Cortadella, Marc Galceran Oms, Michael Kishi...
HPCA
2003
IEEE
15 years 10 months ago
Deterministic Clock Gating for Microprocessor Power Reduction
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Pipeline ba...
Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykuma...
HPCA
2005
IEEE
15 years 3 months ago
Microarchitectural Wire Management for Performance and Power in Partitioned Architectures
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
Rajeev Balasubramonian, Naveen Muralimanohar, Kart...
ICCAD
2006
IEEE
169views Hardware» more  ICCAD 2006»
15 years 6 months ago
Microarchitecture parameter selection to optimize system performance under process variation
Abstract— Design variability due to within-die and die-todie process variations has the potential to significantly reduce the maximum operating frequency and the effective yield...
Xiaoyao Liang, David Brooks