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» Optimizing pipelines for power and performance
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ISVLSI
2008
IEEE
104views VLSI» more  ISVLSI 2008»
15 years 8 months ago
Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations
In high-performance VLSI circuits, the on-chip power densities are playing dominant role due to increased scaling of technology, increasing number of components, frequency and ban...
Prasun Ghosal, Tuhina Samanta, Hafizur Rahaman, Pa...
GLOBECOM
2008
IEEE
15 years 8 months ago
A Low-Signalling Scheme for Distributed Resource Allocation in Multi-Cellular OFDMA Systems
—This paper considers distributed protocol design for joint sub-carrier, transmission scheduling and power management in uplink/downlink multi-cellular OFDMA wireless networks. T...
Pablo Soldati, Mikael Johansson
VLDB
2007
ACM
204views Database» more  VLDB 2007»
15 years 8 months ago
Optimization of Frequent Itemset Mining on Multiple-Core Processor
Multi-core processors are proliferated across different domains in recent years. In this paper, we study the performance of frequent pattern mining on a modern multi-core machine....
Eric Li, Li Liu
DATE
2006
IEEE
87views Hardware» more  DATE 2006»
15 years 8 months ago
Thermal resilient bounded-skew clock tree optimization methodology
The existence of non-uniform thermal gradients on the substrate in high performance IC’s can significantly impact the performance of global on-chip interconnects. This issue is...
Ashutosh Chakraborty, Prassanna Sithambaram, Karth...
RECOMB
2000
Springer
15 years 5 months ago
Sequencing-by-hybridization at the information-theory bound: an optimal algorithm
In a recent paper (Preparata et al., 1999) we introduced a novel probing scheme for DNA sequencing by hybridization (SBH). The new gapped-probe scheme combines natural and univers...
Franco P. Preparata, Eli Upfal