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» Optimizing pipelines for power and performance
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88
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HPCA
2008
IEEE
15 years 10 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
ISQED
2009
IEEE
124views Hardware» more  ISQED 2009»
15 years 4 months ago
Revisiting the linear programming framework for leakage power vs. performance optimization
— This paper revisits and extends a general linear programming(LP) formulation to exploit multiple knobs such as multi-Lgate footprint-compatible libraries and post-layout Lgateb...
Kwangok Jeong, Andrew B. Kahng, Hailong Yao
ANCS
2006
ACM
15 years 3 months ago
CAMP: fast and efficient IP lookup architecture
A large body of research literature has focused on improving the performance of longest prefix match IP-lookup. More recently, embedded memory based architectures have been propos...
Sailesh Kumar, Michela Becchi, Patrick Crowley, Jo...
ICCD
2007
IEEE
183views Hardware» more  ICCD 2007»
15 years 6 months ago
Constraint satisfaction in incremental placement with application to performance optimization under power constraints
We present new techniques for explicit constraint satisfaction in the incremental placement process. Our algorithm employs a Lagrangian Relaxation (LR) type approach in the analyt...
Huan Ren, Shantanu Dutt
76
Voted
DATE
2008
IEEE
131views Hardware» more  DATE 2008»
15 years 4 months ago
Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints
Sleep transistor insertion is one of today’s most promising and widely adopted solutions for controlling stand-by leakage power in nanometer circuits. Although single-cycle powe...
Andrea Calimera, Luca Benini, Enrico Macii