2048 search results - page 37 / 410 » Optimizing pipelines for power and performance |
151
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VLSID
2005
IEEE
16 years 1 months ago
2005
IEEE
Abstract--Power analysis early in the design cycle is critical for the design of lowpower systems. With the move to system-level specifications and design methodologies, there has ...
DATE
2005
IEEE
15 years 7 months ago
2005
IEEE
In this paper, we investigate the impact of Tox and Vth on power performance trade-offs for on-chip caches. We start by examining the optimization of the various components of a s...
166
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TMC
2012
13 years 3 months ago
2012
—We develop a distributed throughput-optimal power allocation algorithm in wireless networks. The study of this problem has been limited due to the nonconvexity of the underlying...
106
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GLVLSI
2009
IEEE
15 years 8 months ago
2009
IEEE
In the context of nanoscale networks-on-chip (NoCs), each link implementation solution is not just a specific synthesis optimization technique with local performance and power im...
HIPEAC
2010
Springer
15 years 10 months ago
2010
Springer
We address the problem of performance and power-efficient thread allocation in a CMP. To that end, based on analytical model, we introduce a parameterized performance/power metric ...