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» Optimizing pipelines for power and performance
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LCTRTS
2007
Springer
15 years 3 months ago
Enabling compiler flow for embedded VLIW DSP processors with distributed register files
High-performance and low-power VLIW DSP processors are increasingly deployed on embedded devices to process video and multimedia applications. For reducing power and cost in desig...
Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Y...
JUCS
2007
102views more  JUCS 2007»
14 years 9 months ago
The Use of Runtime Reconfiguration on FPGA Circuits to Increase the Performance of the AES Algorithm Implementation
: This article presents an architecture that encrypts data with the AES algorithm. This architecture can be implemented on the Xilinx Virtex II FPGA family, by applying pipelining ...
Oscar Pérez, Yves Berviller, Camel Tanougas...
IEICET
2006
84views more  IEICET 2006»
14 years 9 months ago
How to Maximize Software Performance of Symmetric Primitives on Pentium III and 4
Abstract. This paper discusses the state-of-the-art software optimization methodology for symmetric cryptographic primitives on Pentium III and 4 processors. We aim at maximizing s...
Mitsuru Matsui, Sayaka Fukuda
SIGGRAPH
2010
ACM
15 years 2 months ago
Reducing shading on GPUs using quad-fragment merging
Current GPUs perform a significant amount of redundant shading when surfaces are tessellated into small triangles. We address this inefficiency by augmenting the GPU pipeline to...
Kayvon Fatahalian, Solomon Boulos, James Hegarty, ...
ICC
2007
IEEE
125views Communications» more  ICC 2007»
15 years 1 months ago
Increasing Power Efficiency in Transmitter Diversity Systems under Error Performance Constraints
Motivated by combinatorial optimization theory, we propose an algorithmic power allocation method that minimizes the total transmitting power in transmitter diversity systems, prov...
Diomidis S. Michalopoulos, Athanasios S. Lioumpas,...