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» Optimizing pipelines for power and performance
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FCCM
2006
IEEE
111views VLSI» more  FCCM 2006»
15 years 5 months ago
Pipelined Mixed Precision Algorithms on FPGAs for Fast and Accurate PDE Solvers from Low Precision Components
FPGAs are becoming more and more attractive for high precision scientific computations. One of the main problems in efficient resource utilization is the quadratically growing r...
Robert Strzodka, Dominik Göddeke
ICPP
2005
IEEE
15 years 5 months ago
Filter Decomposition for Supporting Coarse-Grained Pipelined Parallelism
We consider the filter decomposition problem in supporting coarse-grained pipelined parallelism. This form of parallelism is suitable for data-driven applications in scenarios wh...
Wei Du, Gagan Agrawal
GLVLSI
2007
IEEE
166views VLSI» more  GLVLSI 2007»
15 years 3 months ago
Efficient pipelining for modular multiplication architectures in prime fields
This paper presents a pipelined architecture of a modular Montgomery multiplier, which is suitable to be used in public key coprocessors. Starting from a baseline implementation o...
Nele Mentens, Kazuo Sakiyama, Bart Preneel, Ingrid...
DAC
2003
ACM
16 years 24 days ago
Power-aware issue queue design for speculative instructions
Speculatively issued instructions may be particularly sensitive to increases in pipeline depth. Our results indicate that as pipeline depth increases, speculation increases the pe...
Tali Moreshet, R. Iris Bahar
FPGA
1999
ACM
174views FPGA» more  FPGA 1999»
15 years 4 months ago
Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs
Pipelining of data path structures increases the throughput rate at the expense of enlarged resource usage and latency unless architectures optimized towards specific applications...
Peter Kollig, Bashir M. Al-Hashimi