2048 search results - page 43 / 410 » Optimizing pipelines for power and performance |
FPGA
2003
ACM
15 years 5 months ago
2003
ACM
We present a pipelining-aware router for FPGAs. The problem of routing pipelined signals is different from the conventional FPGA routing problem. For example, the two terminal N-D...
FPL
1995
Springer
15 years 3 months ago
1995
Springer
Although the energy required to perform a logic operation has continuously dropped at least by ten orders of magnitude since early vacuumtube electronics [1], the increasing clock ...
MICRO
1997
IEEE
15 years 3 months ago
1997
IEEE
Profile data is valuable for identifying performance bottlenecks and guiding optimizations. Periodic sampling of a processor's performance monitoring hardware is an effective...
CGO
2004
IEEE
15 years 3 months ago
2004
IEEE
Traditionally, software pipelining is applied either to the innermost loop of a given loop nest or from the innermost loop to the outer loops. In a companion paper, we proposed a ...
AUTOID
2005
IEEE
15 years 5 months ago
2005
IEEE
This paper presents a novel low power and high performance analog front end circuit for passive RFID transponder. With a novel architecture including three rectifier circuits, amo...