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» Optimizing pipelines for power and performance
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WMPI
2004
ACM
15 years 7 months ago
Addressing mode driven low power data caches for embedded processors
The size and speed of first-level caches and SRAMs of embedded processors continue to increase in response to demands for higher performance. In power-sensitive devices like PDAs a...
Ramesh V. Peri, John Fernando, Ravi Kolagotla
ISCA
2002
IEEE
102views Hardware» more  ISCA 2002»
15 years 6 months ago
Implementing Optimizations at Decode Time
The number of pipeline stages separating dynamic instruction scheduling from instruction execution has increased considerably in recent out-of-order microprocessor implementations...
Ilhyun Kim, Mikko H. Lipasti
ASPDAC
2006
ACM
140views Hardware» more  ASPDAC 2006»
15 years 7 months ago
A near optimal deblocking filter for H.264 advanced video coding
- We propose a near optimal hardware architecture for deblocking filter in H.264/MPEG-4 AVC. We propose a novel filtering order and a data reuse strategy that result in significant...
Shen-Yu Shih, Cheng-Ru Chang, Youn-Long Lin
SBCCI
2005
ACM
111views VLSI» more  SBCCI 2005»
15 years 7 months ago
Total leakage power optimization with improved mixed gates
Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness ...
Frank Sill, Frank Grassert, Dirk Timmermann
ICC
2008
IEEE
117views Communications» more  ICC 2008»
15 years 8 months ago
Proactive Power Optimization of Sensor Networks
—We propose a reduced-complexity genetic algorithm for dynamic deployment of resource constrained multi-hop mobile sensor networks. The goal of this paper is to achieve optimal c...
Rahul Khanna, Huaping Liu, Hsiao-Hwa Chen