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» Optimizing pipelines for power and performance
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TWC
2008
194views more  TWC 2008»
15 years 1 months ago
Optimal Power Scheduling for Correlated Data Fusion in Wireless Sensor Networks via Constrained PSO
Optimal power scheduling for distributed detection in a Gaussian sensor network is addressed for both independent and correlated observations. We assume amplify-and-forward local p...
Thakshila Wimalajeewa, Sudharman K. Jayaweera
GLOBECOM
2009
IEEE
15 years 8 months ago
Joint Power Control and Beamforming Codebook Design for MISO Channels with Limited Feedback
Abstract— This paper investigates the joint design and optimization of the power control and beamforming codebooks for the single-user multiple-input single-output (MISO) wireles...
Behrouz Khoshnevis, Wei Yu
JSA
2008
142views more  JSA 2008»
15 years 1 months ago
A Java processor architecture for embedded real-time systems
Architectural advancements in modern processor designs increase average performance with features such as pipelines, caches, branch prediction, and out-of-order execution. However...
Martin Schoeberl
DAC
2004
ACM
16 years 2 months ago
A method for correcting the functionality of a wire-pipelined circuit
As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...
Vidyasagar Nookala, Sachin S. Sapatnekar
CLUSTER
2000
IEEE
15 years 6 months ago
Design and Performance of Maestro Cluster Network
Most clusters so far have used WAN or LAN-based network products for communication due to their market availability. However, they do not always match communication patterns in cl...
Shinichi Yamagiwa, Munehiro Fukuda, Koichi Wada