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» Optimizing pipelines for power and performance
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CDES
2006
240views Hardware» more  CDES 2006»
15 years 3 months ago
Design of Low Power 4-Tap 8-Bit Adiabatic FIR Filter
Abstract-- Digital signal processing (DSP) is used to perform filtering, decimation and down conversion in common communications systems, like in oversampling analog to digital con...
Arun N. Chandorkar, Gurvinder Singh
129
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CASES
2006
ACM
15 years 5 months ago
Power efficient branch prediction through early identification of branch addresses
Ever increasing performance requirements have elevated deeply pipelined architectures to a standard even in the embedded processor domain, requiring the incorporation of dynamic b...
Chengmo Yang, Alex Orailoglu
ICCAD
2003
IEEE
111views Hardware» more  ICCAD 2003»
15 years 10 months ago
Simultaneous Analytic Area and Power Optimization for Repeater Insertion
We present an analytic formula for repeater insertion in global interconnects that simultaneously minimizes silicon device area and power dissipation for a given performance qrj,/...
Giuseppe S. Garcea, N. P. van der Meijs, Ralph H. ...
ASYNC
2005
IEEE
174views Hardware» more  ASYNC 2005»
15 years 7 months ago
Delay Insensitive Encoding and Power Analysis: A Balancing Act
Unprotected cryptographic hardware is vulnerable to a side-channel attack known as Differential Power Analysis (DPA). This attack exploits data-dependent power consumption of a co...
Konrad J. Kulikowski, Ming Su, Alexander B. Smirno...
ISPASS
2003
IEEE
15 years 6 months ago
Interplay of energy and performance for disk arrays running transaction processing workloads
The growth of business enterprises and the emergence of the Internet as a medium for data processing has led to a proliferation of applications that are server-centric. The power ...
Sudhanva Gurumurthi, Jianyong Zhang, Anand Sivasub...