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» Optimizing pipelines for power and performance
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LCTRTS
2010
Springer
14 years 11 months ago
Improving both the performance benefits and speed of optimization phase sequence searches
The issues of compiler optimization phase ordering and selection present important challenges to compiler developers in several domains, and in particular to the speed, code size,...
Prasad A. Kulkarni, Michael R. Jantz, David B. Wha...
ISVLSI
2002
IEEE
174views VLSI» more  ISVLSI 2002»
15 years 6 months ago
Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits
With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits ha...
Alice Wang, Anantha Chandrakasan, Stephen V. Koson...
ISLPED
1995
ACM
108views Hardware» more  ISLPED 1995»
15 years 5 months ago
Electroid-oriented adiabatic switching circuits
A dual-rail CMOS adiabatic switching circuit approach is described which follows the electroid model of Hall. These circuits can operate in either the retractile cascade or the re...
David J. Frank, Paul M. Solomon
JEA
2008
120views more  JEA 2008»
15 years 1 months ago
Better external memory suffix array construction
Suffix arrays are a simple and powerful data structure for text processing that can be used for full text indexes, data compression, and many other applications in particular in b...
Roman Dementiev, Juha Kärkkäinen, Jens M...
IEEEPACT
2002
IEEE
15 years 6 months ago
Optimizing Loop Performance for Clustered VLIW Architectures
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
Yi Qian, Steve Carr, Philip H. Sweany