2048 search results - page 85 / 410 » Optimizing pipelines for power and performance |
JSAC
2006
15 years 1 months ago
2006
Abstract--In this paper, we present an unequal power allocation technique to increase the throughput of code-division multiple-access (CDMA) systems with chip-level interleavers. P...
TC
2002
15 years 1 months ago
2002
Two architectures and VLSI implementations of the AES Proposal, Rijndael, are presented in this paper. These alternative architectures are operated both for encryption and decrypti...
170
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ICCD
2011
IEEE
14 years 1 months ago
2011
IEEE
—A key challenge in chip multiprocessor (CMP) design is to optimize the performance within a power budget limited by the CMP’s cooling, packaging, and power supply capacities. ...
114
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VTC
2008
IEEE
15 years 8 months ago
2008
IEEE
—The design of LTE turbo coding chain suitable for flexible parallel and pipelined hardware implementations is presented. The hierarchical data structure further offers an opport...
111
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DATE
2004
IEEE
15 years 5 months ago
2004
IEEE
This paper presents a versatile hardware/software cosimulation and co-design environment for embedded 3D graphics accelerators. The GRAphics AcceLerator design exploration framewo...