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» Optimizing pipelines for power and performance
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MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
15 years 7 months ago
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cor...
Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, P...
ISCA
2000
IEEE
156views Hardware» more  ISCA 2000»
15 years 6 months ago
CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit
Reconfigurable hardware has the potential for significant performance improvements by providing support for application−specific operations. We report our experience with Chimae...
Zhi Alex Ye, Andreas Moshovos, Scott Hauck, Prithv...
IJCNN
2007
IEEE
15 years 8 months ago
DHP-Based Wide-Area Coordinating Control of a Power System with a Large Wind Farm and Multiple FACTS Devices
—Wide-area coordinating control is becoming an important issue and a challenging problem in the power industry. This paper proposes a novel optimal wide-area monitor and wide-are...
Wei Qiao, Ronald G. Harley, Ganesh K. Venayagamoor...
LCPC
2004
Springer
15 years 7 months ago
HiLO: High Level Optimization of FFTs
As computing platforms become more and more complex, the task of optimizing performance critical codes becomes more challenging. Recently, more attention has been focused on automa...
Nick Rizzolo, David A. Padua
DAGSTUHL
2007
15 years 3 months ago
Compiler-based Software Power Peak Elimination on Smart Card Systems
Abstract. RF-powered smart cards are widely used in different application areas today. For smart cards not only performance is an important attribute, but also the power consumed ...
Matthias Grumer, Manuel Wendt, Christian Steger, R...