2048 search results - page 9 / 410 » Optimizing pipelines for power and performance |
ISLPED
2003
ACM
15 years 2 months ago
2003
ACM
The increase in high-performance microprocessor power consumption is due in part to the large power overhead of wideissue, highly speculative cores. Microarchitectural speculation...
GLVLSI
2003
IEEE
15 years 2 months ago
2003
IEEE
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
ISLPED
2004
ACM
15 years 3 months ago
2004
ACM
This paper re-examines the well established clocking principles of pipelines. It is observed that clock gating techniques that have long been assumed optimal in reality produce a ...
MICRO
2003
IEEE
15 years 2 months ago
2003
IEEE
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...
ICPP
2002
IEEE
15 years 2 months ago
2002
IEEE
Code size expansion of software-pipelined loops is a critical problem for DSP systems with strict code size constraint. Some ad-hoc code size reduction techniques were used to try...