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DATE
2010
IEEE
118views Hardware» more  DATE 2010»
14 years 10 months ago
Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network
Abstract—On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its to...
Minje Jun, Sungroh Yoon, Eui-Young Chung
NAR
2011
267views Computer Vision» more  NAR 2011»
14 years 6 months ago
EcoCyc: a comprehensive database of Escherichia coli biology
EcoCyc (http://EcoCyc.org) is a comprehensive model organism database for Escherichia coli K-12 MG1655. From the scientific literature, EcoCyc captures the functions of individual...
Ingrid M. Keseler, Julio Collado-Vides, Alberto Sa...
POPL
2007
ACM
16 years 2 days ago
Preferential path profiling: compactly numbering interesting paths
Path profiles provide a more accurate characterization of a program's dynamic behavior than basic block or edge profiles, but are relatively more expensive to collect. This h...
Kapil Vaswani, Aditya V. Nori, Trishul M. Chilimbi
CODES
2008
IEEE
15 years 6 months ago
Speculative DMA for architecturally visible storage in instruction set extensions
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Ch...
SASP
2008
IEEE
183views Hardware» more  SASP 2008»
15 years 6 months ago
Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor
Different approaches have been proposed over the years for automatically transforming High-Level-Languages (HLL) descriptions of applications into custom hardware implementations. ...
Alexandros Papakonstantinou, Deming Chen, Wen-mei ...