867 search results - page 56 / 174 » Optimizing synthesis with metasketches |
131
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ISQED
2010
IEEE
15 years 7 months ago
2010
IEEE
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
93
Voted
SAC
2004
ACM
15 years 6 months ago
2004
ACM
Clustered L0 buffers are an interesting alternative to reduce energy consumption in the instruction memory hierarchy of embedded VLIW processors. Currently, the synthesis of L0 cl...
128
Voted
DATE
2006
IEEE
15 years 6 months ago
2006
IEEE
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
116
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ISQED
2011
IEEE
14 years 4 months ago
2011
IEEE
Due to the dramatic increase in design complexity, verifying the functional correctness of a circuit is becoming more difficult. Therefore, bugs may escape all verification effo...
DATE
2000
IEEE
15 years 4 months ago
2000
IEEE
We present an approach to bus access optimization and schedulability analysis for the synthesis of hard real-time distributed embedded systems. The communication model is based on...