1990 search results - page 105 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
150
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ISCA
2010
IEEE
15 years 6 months ago
2010
IEEE
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
192
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LCTRTS
2001
Springer
15 years 8 months ago
2001
Springer
Phase-decoupled methods for code generation are the state of the art in compilers for standard processors but generally produce code of poor quality for irregular target architect...
225
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ICDE
2005
IEEE
16 years 5 months ago
2005
IEEE
A popular architecture for enterprise applications is one of a stateless object-based server accessing persistent data through Object-Relational mapping software. The reported ben...
135
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VEE
2006
ACM
15 years 10 months ago
2006
ACM
Many new Java runtime optimizations report relatively small, single-digit performance improvements. On modern virtual and actual hardware, however, the performance impact of an op...
230
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ICDE
2006
IEEE
16 years 5 months ago
2006
IEEE
To use their pool of resources efficiently, distributed stream-processing systems push query operators to nodes within the network. Currently, these operators, ranging from simple...