1990 search results - page 112 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
146
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PACT
2007
Springer
15 years 10 months ago
2007
Springer
Abstract. It has been already verified that hardware-supported finegrain synchronization provides a significant performance improvement over coarse-grained synchronization mecha...
129
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FPGA
2004
ACM
15 years 9 months ago
2004
ACM
Moore’s Law states that the number of transistors on a device doubles every two years; however, it is often (mis)quoted based on its impact on CPU performance. This important co...
139
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GLVLSI
2010
IEEE
15 years 9 months ago
2010
IEEE
Flash Memory is a desirable candidate for main memory replacement in embedded systems due to its low leakage power consumption, higher density and non-volatility characteristics. ...
147
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JEC
2006
15 years 4 months ago
2006
This paper explores power consumption for destructive-read embedded DRAM. Destructive-read DRAM is based on conventional DRAM design, but with sense amplifiers optimized for lower ...
143
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DSN
2006
IEEE
15 years 10 months ago
2006
IEEE
—Multithreaded servers with cache-coherent shared memory are the dominant type of machines used to run critical network services and database management systems. To achieve the h...