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HPCA
2000
IEEE
15 years 8 months ago
Design of a Parallel Vector Access Unit for SDRAM Memory Systems
We are attacking the memory bottleneck by building a “smart” memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting appl...
Binu K. Mathew, Sally A. McKee, John B. Carter, Al...
140
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JSA
2008
91views more  JSA 2008»
15 years 4 months ago
Using supplier locality in power-aware interconnects and caches in chip multiprocessors
Conventional snoopy-based chip multiprocessors take an aggressive approach broadcasting snoop requests to all nodes. In addition each node checks all received requests. This appro...
Ehsan Atoofian, Amirali Baniasadi
ICPP
2009
IEEE
15 years 2 months ago
A Resource Optimized Remote-Memory-Access Architecture for Low-latency Communication
This paper introduces a new highly optimized architecture for remote memory access (RMA). RMA, using put and get operations, is a one-sided communication function which amongst ot...
Mondrian Nüssle, Martin Scherer, Ulrich Br&uu...
FAST
2010
15 years 6 months ago
Efficient Object Storage Journaling in a Distributed Parallel File System
Journaling is a widely used technique to increase file system robustness against metadata and/or data corruptions. While the overhead of journaling can be masked by the page cache...
Sarp Oral, Feiyi Wang, David Dillow, Galen M. Ship...
ICDCS
2005
IEEE
15 years 10 months ago
Network-Centric Buffer Cache Organization
A pass-through server such as an NFS server backed by an iSCSI[1] storage server only passes data between the storage server and NFS clients. Ideally it should require at most one...
Gang Peng, Srikant Sharma, Tzi-cker Chiueh