1990 search results - page 143 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
156
click to vote
VLSID
2009
IEEE
16 years 5 months ago
2009
IEEE
Abstract--Digital control for embedded systems often requires low-power, hard real-time computation to satisfy high control-loop bandwidth, low latency, and low-power requirements....
140
click to vote
MICRO
2007
IEEE
15 years 10 months ago
2007
IEEE
This paper describes FAST, a novel simulation methodology that can produce simulators that (i) are orders of magnitude faster than comparable simulators, (ii) are cycleaccurate, (...
133
click to vote
VLSISP
1998
15 years 4 months ago
1998
This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wire...
137
Voted
EUC
2006
Springer
15 years 8 months ago
2006
Springer
As the ever-increasing gap between the speed of processor and the speed of memory has become the cause of one of primary bottlenecks of computer systems, modern architecture system...
125
click to vote
ICS
2005
Tsinghua U.
15 years 10 months ago
2005
Tsinghua U.
Parallel I/O needs to keep pace with the demand of high performance computing applications on systems with ever-increasing speed. Exploiting high-end interconnect technologies to ...