1990 search results - page 147 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
157
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ISLPED
2010
ACM
15 years 4 months ago
2010
ACM
On-chip coherence directories of today's multi-core systems are not energy efficient. Coherence directories dissipate a significant fraction of their power on unnecessary loo...
114
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ISCA
2003
IEEE
15 years 9 months ago
2003
IEEE
Many future shared-memory multiprocessor servers will both target commercial workloads and use highly-integrated “glueless” designs. Implementing low-latency cache coherence i...
127
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FCCM
2006
IEEE
15 years 10 months ago
2006
IEEE
— Many important applications are organized around long-lived, irregular sparse graphs (e.g., data and knowledge bases, CAD optimization, numerical problems, simulations). The gr...
151
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ISPDC
2010
IEEE
15 years 2 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
144
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EUROPAR
2009
Springer
15 years 11 months ago
2009
Springer
An upgrade from dual-core to quad-core AMD processor on the Cray XT system at the Oak Ridge National Laboratory (ORNL) Leadership Computing Facility (LCF) has resulted in significa...