Sciweavers

1990 search results - page 161 / 398
» Optimizing the Instruction Cache Performance of the Operatin...
Sort
View
IEEEINTERACT
2003
IEEE
15 years 9 months ago
High Performance Code Generation through Lazy Activation Records
For call intensive programs, function calls are major bottlenecks during program execution since they usually force register contents to be spilled into memory. Such register to m...
Manoranjan Satpathy, Rabi N. Mahapatra, Siddharth ...
ASAP
2008
IEEE
146views Hardware» more  ASAP 2008»
15 years 11 months ago
A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator
Many complex systems require the use of floating point arithmetic that is exceedingly time consuming to perform on personal computers. However, floating point operators are also h...
Jason Lee, Lesley Shannon, Matthew J. Yedlin, Gary...
ACMMSP
2005
ACM
101views Hardware» more  ACMMSP 2005»
15 years 10 months ago
Transparent pointer compression for linked data structures
64-bit address spaces are increasingly important for modern applications, but they come at a price: pointers use twice as much memory, reducing the effective cache capacity and m...
Chris Lattner, Vikram S. Adve
LCTRTS
1999
Springer
15 years 8 months ago
Effective Exploitation of a Zero Overhead Loop Buffer
A Zero Overhead Loop Buffer (ZOLB) is an architectural feature that is commonly found in DSP processors. This buffer can be viewed as a compiler managed cache that contains a sequ...
Gang-Ryung Uh, Yuhong Wang, David B. Whalley, Sanj...
SAC
2005
ACM
15 years 10 months ago
Performance analysis framework for large software-intensive systems with a message passing paradigm
The launch of new features for mobile phones is increasing and the product life cycle symmetrically decreasing in duration as higher levels of sophistication are reached. Therefor...
Christian Del Rosso