1990 search results - page 174 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
146
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HPCA
1998
IEEE
15 years 9 months ago
1998
IEEE
This paper describes PRISM, a distributed sharedmemory architecture that relies on a tightly integrated hardware and operating system design for scalable and reliable performance....
116
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CORR
2010
Springer
15 years 4 months ago
2010
Springer
Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functio...
129
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DAC
2003
ACM
16 years 5 months ago
2003
ACM
Many embedded systems use a simple pipelined RISC processor for computation and an on-chip SRAM for data storage. We present an enhancement called Intelligent SRAM (ISRAM) that co...
165
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IWDW
2005
Springer
15 years 10 months ago
2005
Springer
Abstract. Many coded digital watermarking systems development requires first the selection of a (uncoded) modulation technique to be part of a coded architecture. Therefore, perfo...
136
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FDL
2005
IEEE
15 years 10 months ago
2005
IEEE
To address performance limitations and expand their applications range, emerging and mature display technologies rely on the design of novel display controllers. Under current mod...