1990 search results - page 181 / 398 » Optimizing the Instruction Cache Performance of the Operatin... |
175
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CODES
2009
IEEE
15 years 11 months ago
2009
IEEE
In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction leve...
169
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IPPS
2009
IEEE
15 years 11 months ago
2009
IEEE
The increasing demand for computational cycles is being met by the use of multi-core processors. Having large number of cores per node necessitates multi-core aware designs to ext...
142
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ISLPED
2004
ACM
15 years 10 months ago
2004
ACM
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...
125
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VTC
2008
IEEE
15 years 11 months ago
2008
IEEE
— This paper addresses advanced radio resource management (RRM) algorithms for multiple-input multipleoutput (MIMO) transmission schemes in downlink OFDMA systems. The analysis c...
172
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TCAD
2008
15 years 4 months ago
2008
Three-dimensional integration has the potential to improve the communication latency and integration density of chip-level multiprocessors (CMPs). However, the stacked highpower de...